A4 Refereed article in a conference publication
Power Optimizations for Transport Triggered SIMD Processors
Authors: Joonas Multanen, Timo Viitanen, Henry Linjamäki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila,
Tommi Zetterman
Editors: Dimitrios Soudris, Luigi Carro
Conference name: International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
Publication year: 2015
Book title : Proceedings: 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)
Journal name in source: Proceedings International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV)
First page : 303
Last page: 309
Number of pages: 7
eISBN: 978-1-4673-7311-1
DOI: https://doi.org/10.1109/SAMOS.2015.7363689
Power consumption in modern processor design is a key aspect. Optimizing the processor for power leads to direct savings in battery energy consumption in case of mobile devices. At the same time, many mobile applications demand high computational performance. In case of large scale computing, low power compute devices help in thermal design and in reducing the electricity bill. This paper presents a case study of a customized low power vector processor design that was synthesized on a 28 nm process technology. The processor has a programmer exposed datapath based on the transport triggered architecture programming model. The paper's focus is on the RTL and microarchitecture level power optimizations applied to the design. Using semiautomated interconnection network and register file optimization algorithm, up to 27% of power savings were achieved. Using this as a baseline and applying register file datapath gating, register file banking and enabling clock gating of individual pipeline stages in pipelined function units, up to 26% of power and energy savings could be achieved with only a 3% area overhead. On top of this, for the measured radio applications, the exposed datapath architecture helped to achieve approximately 18% power improvement in comparison to a VLIW-like architecture by utilizing optimizations unique to transport triggered architectures.
