A4 Refereed article in a conference publication
VeloPix ASIC development for LHCb VELO upgrade
Authors: M van Beuzekom, J Buytaert, M Campbell, P Collins, V Gromov, R Kluit, X Llopart, T Poikela, K Wyllie, V Zivkovic
Editors: Yoshinobu Unno, Hidenori Toyokawa, Yasuo Arai, Takaki Hatsui
Publisher: ELSEVIER SCIENCE BV
Publishing place: AMSTERDAM; PO BOX 211, 1000 AE AMSTERDAM, NETHERLANDS
Publication year: 2013
Journal: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Book title : PIXEL 2012
Journal name in source: Nuclear Instruments & Methods in Physics Research Section A-Accelerators Spectrometers Detectors and Associated Equipment
Journal acronym: Nucl.Instrum.Methods Phys.Res.Sect.A-Accel.Spectrom.Dect.Assoc.Equip.
Volume: 731
First page : 92
Last page: 96
Number of pages: 5
ISSN: 0168-9002
DOI: https://doi.org/10.1016/j.nima.2013.04.016
The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non uniformly distributed over the 2 cm(2) chip area. The chip will incorporate local intelligence in the pixels for Lime-over-threshold measurements, time stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip. (C) 2013 Elsevier B.V. All rights reserved.
