A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era
Tekijät: Haghbayan MH, Miele A, Rahmani AM, Liljeberg P, Tenhunen H
Toimittaja: IEEE
Konferenssin vakiintunut nimi: Design, Automation and Test in Europe Conference and Exhibition
Kustannuspaikka: New York
Julkaisuvuosi: 2016
Kokoomateoksen nimi: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
Tietokannassa oleva lehden nimi: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
Lehden akronyymi: DES AUT TEST EUROPE
Aloitussivu: 854
Lopetussivu: 857
Sivujen määrä: 4
eISBN: 978-3-9815-3707-9
ISSN: 1558-1101
Tiivistelmä
In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.
In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.
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