A4 Vertaisarvioitu artikkeli konferenssijulkaisussa
Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic
Tekijät: Nigussie E, Plosila J, Isoaho J
Konferenssin vakiintunut nimi: 2006 IEEE International Symposium on Circuits and Systems
Julkaisuvuosi: 2006
Journal: IEEE International Symposium on Circuits and Systems. Proceedings
Kokoomateoksen nimi: Proceedings of 2006 IEEE International Symposium on Circuits and Systems
Tietokannassa oleva lehden nimi: 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS
Lehden akronyymi: IEEE INT SYMP CIRC S
Aloitussivu: 2217
Lopetussivu: 2220
Sivujen määrä: 2
ISBN: 978-0-7803-9389-9
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2006.1693060
Tiivistelmä
In this paper we present the circuit implementation of a new asynchronous on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. The link uses a special communication protocol called 2-color 1-phase in which the number of communication actions per transfer is only one, making it potentially faster than the conventional handshake-based protocols. The transceiver circuits are designed using multiple-valued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 90mV voltage swing the power consumption of the link is 16mW for 178ps propagation delay and 2mm interconnect length. The circuit is designed and simulated using Cadence Analog Spectre with a 0.13um CMOS technology.
In this paper we present the circuit implementation of a new asynchronous on-chip link structure, where two modules placed on the opposite sides of the link can exchange data simultaneously. The link uses a special communication protocol called 2-color 1-phase in which the number of communication actions per transfer is only one, making it potentially faster than the conventional handshake-based protocols. The transceiver circuits are designed using multiple-valued current-mode logic, linear summation is implemented by wiring without active devices simplifying the resulting circuitry. By using 90mV voltage swing the power consumption of the link is 16mW for 178ps propagation delay and 2mm interconnect length. The circuit is designed and simulated using Cadence Analog Spectre with a 0.13um CMOS technology.
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