A4 Refereed article in a conference publication
Current mode on-chip interconnect using level-encoded two-phase dual-rail encoding
Authors: Nigussie E, Plosila J, Isoaho J
Conference name: 2007 IEEE International Symposium on Circuits and Systems
Publication year: 2007
Journal: IEEE International Symposium on Circuits and Systems. Proceedings
Book title : Proceedings of 2007 IEEE International Symposium on Circuits and Systems
Journal name in source: 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Journal acronym: IEEE INT SYMP CIRC S
First page : 649
Last page: 652
Number of pages: 4
ISBN: 978-1-4244-0920-4
ISSN: 0271-4302
DOI: https://doi.org/10.1109/ISCAS.2007.377892(external)
Abstract
we present delay variations insensitive long on-chip interconnect implementation based on current mode signaling and Level-Encoded two-phase Dual-Rail (LEDR) encoding. LEDR encoding is chosen over the normal two-phase dual-rail encoding because its completion detection and decoding circuitry is faster and much simpler since detection is level based rather than transition. The communication latency of this interconnect at global lengths of the wires reduces by half compared to conventional voltage mode LEDR interconnect. This is due to current mode signaling, making it possible to achieve high speed without pipelining and/or using repeaters. Performance simulation shows that at 5mm wire length the throughput of this interconnect is 1Gbps per one dual-rail wire pair. The effect of crosstalk on signal propagation delay is analyzed using four-bit parallel data transfer with the worst-case switching pattern and transmission line model which have both capacitive and inductive coupling. The interconnect circuitry is designed and simulated using Cadence Analog Spectre and Hspice with 130nm CMOS technology.
we present delay variations insensitive long on-chip interconnect implementation based on current mode signaling and Level-Encoded two-phase Dual-Rail (LEDR) encoding. LEDR encoding is chosen over the normal two-phase dual-rail encoding because its completion detection and decoding circuitry is faster and much simpler since detection is level based rather than transition. The communication latency of this interconnect at global lengths of the wires reduces by half compared to conventional voltage mode LEDR interconnect. This is due to current mode signaling, making it possible to achieve high speed without pipelining and/or using repeaters. Performance simulation shows that at 5mm wire length the throughput of this interconnect is 1Gbps per one dual-rail wire pair. The effect of crosstalk on signal propagation delay is analyzed using four-bit parallel data transfer with the worst-case switching pattern and transmission line model which have both capacitive and inductive coupling. The interconnect circuitry is designed and simulated using Cadence Analog Spectre and Hspice with 130nm CMOS technology.
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