A4 Refereed article in a conference publication
Analysis of crosstalk and process variations effects on on-chip interconnects
Authors: Nigussie E, Tuuna S, Plosila J, Isoaho J
Conference name: 2006 International Symposium on System-on-Chip
Publication year: 2006
Book title : Proceedings of 2006 International Symposium on System-on-Chip
Journal name in source: 2006 International Symposium on System-on-Chip Proceedings
First page : 163
Last page: 166
Number of pages: 4
ISBN: 978-1-4244-0621-0
DOI: https://doi.org/10.1109/ISSOC.2006.321992
Abstract
we present analysis of crosstalk and process variations effects on reliability and signal propagation delay of two delay-insensitive on-chip interconnects. The first interconnect is designed using conventional two-phase dual-rail encoding using voltage-mode signaling. The second one uses current-mode signaling with new implementation of two-phase dual-rail encoding. It uses multi-current level and differential switching of dual-rail wires to indicate the data value and its validity respectively. Performance comparison between the two interconnects shows the novel differentially switching dual-rail link is faster compared to the conventional two-phase dual-rail one. The effect of crosstalk is analyzed using 4-bit parallel data transfer using transmission line model with capacitive and inductive coupling and 16 different switching patterns. We analyze the effect of process variations on reliability and delay in the presence of crosstalk by changing wire width by +/-10% and thickness by -10%. In addition the effect of +/-3 sigma supply voltage variation on delay is studied. The circuit is designed and simulated using Cadence Analog Spectre and Hspice of 130nm CMOS technology.
we present analysis of crosstalk and process variations effects on reliability and signal propagation delay of two delay-insensitive on-chip interconnects. The first interconnect is designed using conventional two-phase dual-rail encoding using voltage-mode signaling. The second one uses current-mode signaling with new implementation of two-phase dual-rail encoding. It uses multi-current level and differential switching of dual-rail wires to indicate the data value and its validity respectively. Performance comparison between the two interconnects shows the novel differentially switching dual-rail link is faster compared to the conventional two-phase dual-rail one. The effect of crosstalk is analyzed using 4-bit parallel data transfer using transmission line model with capacitive and inductive coupling and 16 different switching patterns. We analyze the effect of process variations on reliability and delay in the presence of crosstalk by changing wire width by +/-10% and thickness by -10%. In addition the effect of +/-3 sigma supply voltage variation on delay is studied. The circuit is designed and simulated using Cadence Analog Spectre and Hspice of 130nm CMOS technology.
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