Tero Säntti
D.Sc. (Tech.)
teansa@utu.fi Joukahaisenkatu 3-5 Turku |
FPGA, Space, Imaging, Radiation, Embedded Systems
D.Sc. (Tech.) in 2008, Microelectronics.
In addition to University stuff, I am also working in industry:
- Aboa Space Research Oy, Senior Engineer, Chairman of the Board
- Kovilta Oy, Lead FPGA Architect
All things related to FPGAs, and especially their use in space and/or in imaging.
- 2010 - 2012, FPGA Prototyping, (5 ECTS)
- 2009 - 2011 Sulautetut prosessorijärjestelmät (Embedded Processor Systems), (5 ECTS)
- 2005 - 2008 Mikroprosessoripohjaiset järjestelmät (Microprocessor Based Systems), (5 ECTS)
- 2007 Embedded Virtual Machines on FPGAs (6 / 3 ECTS), post-graduate level course
- 2006 Special Course on Floating Point Arithmetics, (3 ECTS)
- 2006 Special Course on External Funding, (2 ECTS)
Besides these, I have been participating in teaching of courses in electronics and related fields since 1998, first at Department of Applied Physics and later at Department of Information Technology, both in University of Turku. Most of these have been demonstrations and exercises. Courses include: Microprocessors, Digital Teaching Media, Analog Electronics II, Design of Electronic Equipment, Analog Electronics I, Multimedia Algorithms, LSI Circuit Design, Circuit Theory I and Basic Electronics.
- Tree-Model Based Contention-Aware Task Mapping on Many-Core Networks-on-Chip (2012) Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
(A1 Refereed original research article in a scientific journal) - Tree-Model Based Contention-Aware Task Mapping on Many-Core Network-on-Chips. (2011) IEEE Yang Bo, Guang Liang, Säntti Tero, Plosila Juha
(A4 Refereed article in a conference publication ) - A Dynamic Fault-Tolerant Remapping Algorithm Based on Tree-Model of Network-on-Chip (2010)
- Proceedings : Design, Automation, and Test in Europe Conference and Exhibition
(A4 Refereed article in a conference publication ) - An Improved Hardware Acceleration Scheme for Java Method Calls (2010) Norchip 2010 Säntti T, Tyystjärvi J, Plosila J
(A4 Refereed article in a conference publication ) - Efficient Bytecode Optimizations for a Multicore Java Co-Processor System (2010) 2010 12th Biennial Baltic Electronics Conference (BEC2010) Tyystjärvi J, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Heap Access Optimizations for a Hardware-Accelerated Java Virtual Machine (2010) 2010 International Symposium on System-on-Chip Tyystjärvi J, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Multi-Application Mapping Algorithm for Network-on-Chip Platforms (2010) Proc. of the 26th IEEE Convention of Electrical and Electronics Engineers in Israel (IEEEI) Yang B, Guang L, Xu T C, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Multi-Application Multi-Step Mapping Method for Many-Core Network-on-Chips Platforms (2010) Proc. of the 28th IEEE Norchip Conference (NORCHIP 2010) Yang B, Guang L, Xu T C, Yin A W, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Parallel Performance Evaluation of a Multicore Java Co-Processor System (2010) "DATE 2010 Workshop ""Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications""" Tyystjärvi J, Säntti T, Plosila J
(A4 Refereed article in a conference publication ) - Tree-Model Based Mapping for Energy-Efficient and Low-Latency Network-on-Chip (2010) Proceedings of 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) Yang B, Xu T C, Säntti T, Plosila J
(A4 Refereed article in a conference publication )
