Amleset Kelati
Ph.D. (Tech)

Department of Computing,, Smart Systems


IoT, Security for Communications System, Machine Learning ,Smart gird , System-on-Chip, DSP, embedded system and Embedded HW security, Wireless communications systems, RFIC / ASIC / FPGA design, Verification and Integration,


Amleset Kealti (PH.D Tech) researches  at the Departmennt of Computing, Electronics and smart system lab at the  University of Turku,  Her research interests include on Ultra-low power (ULP) wirelessly networked embedded processor for sensing systems. Her interest lies in establishing a heterogeneous embedded system, a mix general purpose processor for special purpose computing engines and sensor related to smart system technology. Her main expertis is programming, signal processing and ML, and HW implementation. She has working experience from interdisciplinary researchs.

Her research interest is in the area of parallel algorithm design and implementation´of heterogeneous parallel computing on multicores, GPUs, FPGA, ASICs. Experianced in monitoring HPC applications on middleware for the cloud big data applications.    


My postdoctoral research is in department of Astronomy, Finnish Centre for Astronomy with ESO. Her research focus is on implementation of wideband full-stokes spectrometer in FPGA /Casper "Collaboration for Astronomy Signal Processing and Electronic Research.  The implementation is needed for processing of large amount of data communication with high bandwith of the spectromrnter with cost performance. 

My PHD project belong to Department of Computing at smart systems unit ( IoT4Health). The main focus of the research is to develop architecture for Internet of Things (IoT) platform that can be used for monitoring e health by wearable’s and by Smart grid technology.  The tass is to develop the architecture and prototype but also design and implementations of reliable tools for monitoring of an e health system that determine and detect the vital sign of health conditions of patients.


Embedded Hardware Design in ASIC and FPGA .

DSP-Design with HDL

Digital Design


Last updated on 2022-18-06 at 20:00