The Thick Control Flow (TCF) model simplifies parallel programming by
bundling computations with the same control flow into single flows of
variable thickness, and has the prospect of alleviating redundant usage
of software and hardware resources. While architectures that can support
the TCF model have been proposed, current proposals cannot support
concurrent memory accesses that can both simplify programming and speed
up many parallel algorithms by a logarithmic factor. In this paper, we
extend current TCF architectures to efficiently support concurrent read
as well as write memory accesses. The solution is based on bounded size
step-caches, and exploit the two-part, hybrid, frontend-backend
structure of current TCF processors, and synchronization properties of
the TCF model itself. According to our simulation-based evaluation, a
concurrent memory access TCF processor with B backends can execute algorithms with substantial concurrent memory accesses up to B
times faster than a baseline TCF processor not supporting concurrent
memory access. The hardware overhead of the solution is estimated to be
modest. We include parallel program code to illustrate the gains by
supporting concurrent memory accesses.