A4 Artikkeli konferenssijulkaisussa
Adaptive Fault Simulation on Many-core Microprocessor Systems




Julkaisun tekijät: Mohammad-Hashem Haghbayan, Sami Teräväinen, Amir-Mohammad Rahmani, Pasi Liljeberg, Hannu Tenhunen
Julkaisuvuosi: 2015
Kirjan nimi *: 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
ISBN: 978-1-4799-8606-4

Tiivistelmä

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.


Last updated on 2019-29-01 at 10:45