A1 Journal article – refereed
Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors

List of Authors: Grönroos Mika, Nevalainen Tapani, Paasio Ari
Publication year: 2018
Journal: IEEE Transactions on Circuits and Systems II: Express Briefs
Volume number: 65
Issue number: 5
eISSN: 1558-3791


High-speed thermal imaging is necessary in many applications. However,
the traditional column-wise readout implementations reduce the
achievable frame rate. Also, analog integration for each individual
pixel is not possible without sacrificing pixel area. In this brief, we
present an implementation of a fast and low-power pixel-wise readout
circuit scheme with a digital integration method using 65-nm standard
CMOS technology. The power consumption of the readout circuit is up to
15 μW and the layout area is 100 μm × 100 μm. Furthermore, we analyze
our design for non-idealities, such as noise and process mismatches
using a circuit simulator.

Last updated on 2019-29-01 at 13:47