Refereed journal article or data article (A1)

Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors




List of AuthorsGrönroos Mika, Nevalainen Tapani, Paasio Ari

PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Publication year2018

JournalIEEE Transactions on Circuits and Systems II: Express Briefs

Volume number65

Issue number5

Start page537

End page541

Number of pages5

ISSN1549-7747

eISSN1558-3791

DOIhttp://dx.doi.org/10.1109/TCSII.2018.2821898


Abstract

High-speed thermal imaging is necessary in many applications. However,
the traditional column-wise readout implementations reduce the
achievable frame rate. Also, analog integration for each individual
pixel is not possible without sacrificing pixel area. In this brief, we
present an implementation of a fast and low-power pixel-wise readout
circuit scheme with a digital integration method using 65-nm standard
CMOS technology. The power consumption of the readout circuit is up to
15 μW and the layout area is 100 μm × 100 μm. Furthermore, we analyze
our design for non-idealities, such as noise and process mismatches
using a circuit simulator.


Last updated on 2021-24-06 at 10:39