Refereed article in conference proceedings (A4)

Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks




List of AuthorsSergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Hassan Anwar, Juha Plosila, Hannu Tenhunen

Conference nameThe Euromicro confertence on digital system design

Publication year2014

JournalDigital System Design

Start page496

End page503

Number of pages8

ISSN0888-2118

DOIhttp://dx.doi.org/10.1109/DSD.2014.109

URLhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927283


Abstract

Spiking neural networks (SNNs) are the closest approach to biological neurons in comparison with conventional artificial neural networks (ANN). SNNs are composed of neurons and synapses which are interconnected with a complex pattern. As communication in such massively parallel computational systems is getting critical, the network-on-chip (NoC) becomes a promising solution for providing a scalable and robust interconnection fabric. However, using NoC for large-scale SNNs arises a trade-off among scalability, throughput, neuron/router ratio (cluster size), and area overhead. In this paper, we tackle the trade-off using clustering approach and try to optimize the synaptic resources utilization. An optimal cluster size can provide lowest area overhead and power consumption. For the learning purposes, a phenomenon known as spike-timing-dependent plasticity (STDP) is utilized. The micro-architectures of the network, clusters, and the computational neurons are also described. The presented approach suggests a promising solution of integrating NoCs and STDP-based SNNs for the optimal performance based on the underlying application.



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Last updated on 2021-24-06 at 12:05