A4 Article in conference proceedings
Analysing and Modelling the On-chip Traffic of Parallel Applications




List of Authors: Thomas Xu, Jonne Pohjankukka, Ville Leppänen
Publication year: 2016
Book title *: 42th Euromicro Conference on Software Engineering and Advanced Applications, SEAA 2016
Number of pages: 8
ISBN: 978-1-5090-2821-4
eISBN: 978-1-5090-2820-7

Abstract

In this paper, we investigate the traffic characteristics of parallel
and high performance computing applications. Parallel applications that
utilize multiple processing cores are widespread nowadays due to the
trend of multicore processors. However the design paradigm of
traditional sequential execution and concurrent execution can vary
significantly. Therefore the estimation and prediction approaches used
in conventional software can be limited for parallel applications. The
communication among different nodes in a multicore system should be
analysed and categorized in order to improve the accuracy of system
simulation. We study several parallel applications running on a full
system simulation environment. The communication traces among different
nodes are collected and analysed. We discuss the detailed
characteristics of these applications. The applications are grouped into
different categories depending on several parallel programming
paradigms. We apply power-law model with maximum likelihood estimation,
Gaussian mixture model, as well as the polynomial model for fitting the
trace data. A generic synthetic traffic model is proposed based on the
results. Experiments show the proposed model can be used to evaluate the
performance of parallel systems more accurately than by other synthetic
traffic models.


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Last updated on 2019-20-07 at 13:46