A4 Artikkeli konferenssijulkaisussa
Accelerated On-Chip Communication Test Methodology Using a Novel High-Level Fault Model

Julkaisun tekijät: Elmira Karimi, Mohammad-Hashem Haghbayan, Amir-Mohammad Rahmani, Mohmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi
Julkaisuvuosi: 2015
Kirjan nimi *: IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2015, Turin, Italy
Sivujen määrä: 6
ISBN: 978-1-4799-8669-9


A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement.

Last updated on 2019-20-07 at 11:10

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