A1 Journal article – refereed
VeloPix: the pixel ASIC Lfor the LHCb upgrade

List of Authors: Poikela T, De Gaspari M, Plosila J, Westerlund T, Ballabriga R, Buytaert J, Campbell M, Llopart X, Wyllie K, Gromov V, van Beuzekom M, Zivkovic V
Publisher: IOP Publishing LTD
Publication year: 2015
Journal: Journal of Instrumentation
Journal name in source: JOURNAL OF INSTRUMENTATION
Journal acronym: J Instrum
Volume number: 10
ISSN: 1748-0221


VeloPix is a binary pixel readout chip with a data driven readout, designed in 130 nm CMOS technology. The pixels are combined into groups of 2 x 4 super pixels, enabling a shared logic and a reduction of bandwidth due to combined address and time stamp information. The pixel hits are combined with other simultaneous hits in the same super pixel, time stamped, and immediately driven off-chip. The analog front-end must be sufficiently fast to accurately time stamp the data, with a small enough dead time to minimize data loss in the most occupied regions of the chip. The data is driven off chip with a custom designed high speed serialiser. The current status of the ASIC design, the chip architecture and the simulations will be described.

Last updated on 2019-21-08 at 21:00