Refereed journal article or data article (A1)

VeloPix: the pixel ASIC Lfor the LHCb upgrade




List of AuthorsPoikela T, De Gaspari M, Plosila J, Westerlund T, Ballabriga R, Buytaert J, Campbell M, Llopart X, Wyllie K, Gromov V, van Beuzekom M, Zivkovic V

PublisherIOP Publishing LTD

Publication year2015

JournalJournal of Instrumentation

Journal name in sourceJOURNAL OF INSTRUMENTATION

Journal acronymJ Instrum

Article numberARTN C01057

Volume number10

Number of pages10

ISSN1748-0221

DOIhttp://dx.doi.org/10.1088/1748-0221/10/01/C01057


Abstract

VeloPix is a binary pixel readout chip with a data driven readout, designed in 130 nm CMOS technology. The pixels are combined into groups of 2 x 4 super pixels, enabling a shared logic and a reduction of bandwidth due to combined address and time stamp information. The pixel hits are combined with other simultaneous hits in the same super pixel, time stamped, and immediately driven off-chip. The analog front-end must be sufficiently fast to accurately time stamp the data, with a small enough dead time to minimize data loss in the most occupied regions of the chip. The data is driven off chip with a custom designed high speed serialiser. The current status of the ASIC design, the chip architecture and the simulations will be described.



Last updated on 2021-24-06 at 09:26